1. Technical Field
Exemplary embodiments relate to a method of forming an insulation layer pattern, and a method of manufacturing a semiconductor device including an insulation layer pattern. More particularly, example embodiments relate to a method of forming an insulation layer pattern having a minute dimension, and a method of manufacturing a semiconductor device including an insulation layer pattern having a minute dimension.
2. Description of the Related Art
As a degree of integration of a semiconductor device increases, widths of a pattern and a contact in the semiconductor device decrease. However, since a resolution of a photo process is limited, it is difficult to form a minute pattern having a desirably small width and/or a minute opening having a desirably small width in the semiconductor device.
To form a minute contact, a self align contact process that uses an etching selectivity between peripheral patterns and an insulating interlayer has been employed. However, in a case in which a minute opening or a minute pattern is formed in an insulating layer which does not have peripheral patterns, the self align contact process may not be employed.
Alternatively, in order to form an opening having a minute width, an inner spacer may be formed in the opening. However, since it is difficult to uniformly form the inner spacer in the opening, the inner spacer may cause other problems.
Therefore, a method for forming an opening which has a width of about 30 nm, which is less than a resolution limit of the photo process, without causing a defect, may be required.